Negative Capacitance Transistors – Modeling, Simulation and Processor Performance
ECE 595 Department Seminar Series
September 6, 2019
11:00 AM - 12:30 PM
Lecture Center D5
Chicago, IL 60607
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Negative Capacitance Transistors - Modeling, Simulation and Processor Performance
Presenter: Yogesh Singh Chauhan, Indian Institute of Technology Kanpur (IITK)
Abstract: The ongoing scaling of CMOS technology is now reaching its limit, due to supply voltage reduction being restricted by the subthreshold swing (SS) of 60mV/decade achievable at room temperature owing to Boltzmann transport of the charge carriers. Concept of negative capacitance proposed to achieve a sub-60mV/decade SS is currently seen as one of the potential solutions to the problem. A “negative capacitance transistor (NCFET)” employs a ferroelectric material in the gate stack of a FET providing a negative capacitance and thereby an “internal voltage amplification” at the gate of the internal FET which helps in reducing SS. Several experiments have successfully demonstrated an improved SS with the bulk MOSFET, FinFET, and 2D FETs. The improvement in subthreshold characteristics is also accompanied with the advantage of an increased ON current relative to the reference FET as has been observed both in simulation studies and experiments. In this lecture, the physics and modeling of various NCFET structures and impact of this new transistor on circuits including processors will be discussed.
Speaker bio: Y. S. Chauhan is an associate professor at Indian Institute of Technology Kanpur (IITK), India. He was with the Semiconductor Research & Development Center at IBM Bangalore from 2007 to 2010; Tokyo Institute of Technology in 2010; the University of California Berkeley from 2010 to 2012; and ST Microelectronics from 2003 to 2004. Chauhan is the developer of several industry standard models: ASM-GaN-HEMT model, BSIM- BULK model (formerly BSIM6), BSIM-CMG model, and BSIM-IMG model. His research group is involved in developing compact models for GaN transistors, FinFET, Nanosheet/Gate-All-Around FETs, FDSOI transistors, Negative Capacitance FETs and 2D FETs. His research interests are characterization, modeling, and simulation of semiconductor devices.
Chauhan is the editor of IEEE Transactions on Electron Devices, and distinguished lecturer of the IEEE Electron Devices Society. He is the member of IEEE-EDS Compact Modeling Committee, and fellow of Indian National Young Academy of Science (INYAS). He is the founding chairperson of IEEE Electron Devices Society U.P. chapter and vice-chairperson of IEEE U.P. section. He has published more than 200 papers in international journals and conferences.
Chauhan received the Ramanujan fellowship in 2012, IBM faculty award in 2013, P. K. Kelkar fellowship in 2015, and the CNR Rao faculty award, Humboldt fellowship, and Swarnajayanti fellowship in 2018. He has served in the technical program committees of IEEE International Electron Devices Meeting (IEDM), IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), IEEE European Solid-State Device Research Conference (ESSDERC), IEEE Electron Devices Technology and Manufacturing (EDTM), and IEEE International Conference on VLSI Design and International Conference on Embedded Systems.
Faculty Host: Professor Amit Trivedi, email@example.com
Oct 9, 2019
Oct 9, 2019