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Mar 18 2022

Design automation for correct, fast, and reliable heterogeneous computing systems


March 18, 2022

9:45 AM - 11:00 AM


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Design automation for correct, fast, and reliable heterogeneous computing systems

Presenter: Debjit Pal, Cornell University

Abstract: With the end of Dennard scaling and the looming end of Moore’s law, we are moving into a computing era increasingly reliant upon specialization and heterogeneity for continued performance improvements. In the next decade, special-purpose hardware accelerators and heterogeneous systems will be the computing backbone for high-impact emergent applications, such as autonomous vehicles and genomics. However, with rapidly shrinking time-to-market and moving application targets, traditional design automation techniques are futile to deliver the desired correct system functionality and performance at pace for heterogeneous and specialized hardware.

In this talk, hear an overview of Pal's contributions to design automation techniques to enable correct, fast, and reliable heterogeneous computing systems. First, his novel work on post-silicon functional validation of System-on-Chips (SoCs) will be discussed. Elegant, scalable, systematic, and industrially viable framework for post-silicon SoC validation will be presented. A fundamental flaw in decade-long academic research of post-silicon validation and provided new insights to the community for future post-silicon validation research will be presented. Also, PolyCL, a polyhedral analysis-based verification methodology to verify a hardware accelerator design written in a domain-specific language (DSL) that allows decoupling of user-specified hardware optimizations from an algorithm will be presented. PolyCL automatically verifies 1) the legality of the user-specified hardware optimizations (i.e., compute customizations) and 2) the correctness of the generated code. PolyCL either proves the correctness of such optimization sequence and the generated code or generates helpful feedback for the user for debugging, thereby increasing productivity and agility of hardware accelerator development. Finally, Pal's future research vision on how we should think, design, and rapidly develop specialized and heterogeneous computing systems to meet the computing needs of new emergent applications will be presented.

Speaker bio: Pal is a post-doctoral researcher in the school of electrical and computer engineering at Cornell University. He received his PhD from the University of Illinois at Urbana-Champaign, his masters degree from IIT Kharagpur, and his bachelors degree from Jadavpur University. His research focuses on new algorithms, methodologies, and design automation tools for building correct and reliable heterogeneous computing systems via synergistic applications of specification, architecture, and validation technologies. Specifically, his recent publications focus on post-silicon and pre-silicon validation of system-on-chips, application of machine learning for high-level synthesis and hardware resiliency, and security validation. He is the lead developer of the popular automatic assertion generation tool, GoldMine, which many leading semiconductor companies have licensed for internal use and has been used widely in academia. His research has received IEEE CEDA Student Research Award 2016 and three best paper nominations at ICCAD'15, DAC'18, and ASP-DAC'19, respectively.

Faculty Host: Inna Partin-Vaisband,

This lecture will not be recorded.


ECE Student Affairs

Date posted

Mar 18, 2022

Date updated

Mar 18, 2022