Design Automation for Correct, Fast, and Reliable Heterogeneous Computing Systems
ECE 595 Department Seminar Series
September 16, 2022
11:00 AM - 12:15 PM
Location
UIC Lecture Center C1
Address
802 S Halsted St, Chicago, IL 60607
Calendar
Download iCal FileDesign Automation for Correct, Fast, and Reliable Heterogeneous Computing Systems
Speaker: Debit Pal, UIC
Abstract: With the end of Dennard scaling and the looming end of Moore’s law, we are moving into a computing era increasingly reliant upon specialization and heterogeneity for continued performance improvements. In the next decade, special-purpose hardware accelerators and heterogeneous systems will be the computing backbone for high-impact emergent applications, such as autonomous vehicles and genomics. However, with rapidly shrinking time-to-market and moving application targets, traditional design automation techniques are futile to deliver the desired correct system functionality and performance at pace for heterogeneous and specialized hardware.
In this talk, I shall discuss an overview of my contributions to design automation techniques to enable correct, fast, and reliable heterogeneous computing systems. First, I shall discuss our novel work on post-silicon functional validation of System-on-Chips (SoCs). I shall present our elegant, scalable, systematic, and industrially viable framework for post-silicon SoC validation. Our work uncovered a fundamental flaw in decade-long academic research of post-silicon validation and provided new insights to the community for future post-silicon validation research. Next, I shall discuss PolyCL, a polyhedral analysis-based verification methodology to verify a hardware accelerator design written in a domain-specific language (DSL) that allows decoupling of user-specified hardware optimizations from an algorithm. PolyCL automatically verifies 1) the legality of the user-specified hardware optimizations (i.e., compute customizations) and 2) the correctness of the generated code. PolyCL either proves the correctness of such optimization sequence and the generated code or generates helpful feedback for the user for debugging, thereby increasing productivity and agility of hardware accelerator development. Finally, I shall conclude with my future research vision on how we should think, design, and rapidly develop specialized and heterogeneous computing systems to meet the computing needs of new emergent applications.
Speaker bio: Debjit Pal is an assistant professor in the electrical and computer engineering department at UIC. Prior to joining UIC, Pal was a post-doctoral associate in the electrical and computer engineering department at Cornell University. He received his Ph.D. from the University of Illinois at Urbana-Champaign, masters's degree from IIT Kharagpur, and bachelors degree from Jadavpur University, India. His research focuses on new algorithms, methodologies, and design automation tools for building correct and reliable heterogeneous computing systems via synergistic applications of specification, architecture, and validation technologies. Specifically, his recent publications focus on post-silicon and pre-silicon validation of System-on-Chips, application of machine learning for high-level synthesis and hardware resiliency, and security validation. Pal is the lead developer of the popular automatic assertion generation tool, GoldMine, which many leading semiconductor companies have licensed for internal use and has been used widely in academia. His research has received IEEE CEDA Student Research Award 2016 and three best paper nominations at ICCAD'15, DAC'18, and ASP-DAC'19, respectively.
Faculty host: Igor Paprotny, paptrotny@uic.edu
This lecture will also be available online; please contact department for login.
Date posted
Sep 22, 2022
Date updated
Sep 22, 2022