Publications

Kun Fang, Hongzhong Zheng, and Zhichun Zhu, Heterogeneous mini-rank: Adaptive, power-efficient memory architecture. In Proceedings of the 2010 International Conference on Parallel Processing, San Diego, CA, September 2010.

Hongzhong Zheng and Zhichun Zhu, Power and Performance Trade-Offs in Contemporary DRAM System Designs for Multicore Processors, IEEE Transactions on Computers. Vol. 59, No. 8, August 2010, pp. 1033-1046.

Hongzhong Zheng, Jiang Lin, Zhao Zhang and Zhichun Zhu, Decoupled DIMM: Building high-bandwidth memory system using low-speed DRAM devices. In Proceedings of the 36th Annual International Symposium on Computer Architecture, Austin, TX, June 2009, pp. 255-265.

Hongzhong Zheng, Jiang Lin, Zhao Zhang, Eugene Gorbatov, Howard David and Zhichun Zhu, Mini-rank: adaptive DRAM architecture for improving memory power efficiency. In Proceedings of the 41st IEEE/ACM International Symposium on Microarchitecture, Lake Como, Italy, November 2008, pp. 210-221.

Hongzhong Zheng, Jiang Lin, Zhao Zhang and Zhichun Zhu, Memory access scheduling schemes for systems with multi-ore processors. In Proceedings of the 2008 International Conference on Parallel Processing, Portland, OR, September 2008.

Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Eugene Gorbatov, Howard David and Zhao Zhang, Software thermal management of DRAM memory for multicore systems. In Proceedings of the 2008 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, Annapolis, MD, June 2008, pp. 337-348.

Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Howard David and Zhao Zhang, Thermal modeling and management of DRAM memory systems. In Proceedings of the 34th International Symposium on Computer Architecture, San Diego, CA, June 2007, pp. 312-322.

Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Zhao Zhang and Howard David, DRAM-level prefetching for fully-buffered DIMM: design, performance and power saving. In Proceedings of the 2007 IEEE International Symposium on Performance Analysis of Systems and Software, San Jose, CA, April 2007, pp 94-104.

Zhichun Zhu and Xiaodong Zhang, Look-ahead architecture adaptation to reduce processor power consumption, IEEE Micro, Vol. 25, No. 4, 2005, pp. 10-19.

Zhichun Zhu and Zhao Zhang, A performance comparison of DRAM memory system optimizations for SMT processors, In Proceedings of the 11th International Symposium on High-Performance Computer Architecture, San Francisco, CA, February 2005, pp. 213-224.

Zhao Zhang, Zhichun Zhu, and Xiaodong Zhang, Design and Optimization of Large Size and Low Overhead Off-Chip Caches, IEEE Transactions of Computers, Vol. 53, No. 7, July, 2004, pp. 843-855.

Zhichun Zhu and Xiaodong Zhang, Access Mode Predictions for Low Power Cache Design. IEEE Micro, Vol. 22, No. 2, March/April, 2002, pp. 58-71.

Zhichun Zhu, Zhao Zhang, and Xiaodong Zhang, Fine-grain priority scheduling on multiple-channel memory systems. In Proceedings of the 8th International Symposium on High-Performance Computer Architecture, Cambridge, MA, February 2002, pp. 107-116.

Zhao Zhang, Zhichun Zhu, and Xiaodong Zhang, Breaking address mapping symmetry at multi-levels of memory hierarchy to reduce DRAM row-buffer conflicts. Journal of Instruction-level Parallelism (JILP), Vol. 3, October 2001.

Zhao Zhang, Zhichun Zhu, and Xiaodong Zhang, Cached DRAM for ILP processor memory access latency reduction. IEEE Micro, Vol. 21, No. 4, July/August, 2001, pp. 22-32.

Zhao Zhang, Zhichun Zhu, and Xiaodong Zhang, A Permutation-based Page Interleaving Scheme to Reduce Row-buffer Conflicts and Exploit Data Locality. In Proceedings of 33rd Annual International Symposium on Microarchitecture, Monterey, California, December 2000, pp. 32-41.

Xing Du, Xiaodong Zhang, Zhichun Zhu, Memory hierarchy considerations for cost-effective cluster computing, IEEE Transactions on Computers, Vol. 49, No. 9, September 2000, pp. 915-933.

Xiaodong Zhang, Zhichun Zhu, Xing Du, Analysis of commercial workload on SMP multiprocessors. Performance'99 (extended abstract), August 1999.